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參數(shù)資料
| 型號(hào)： | 74LV86 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad 2-input EXCLUSIVE-OR gate(四2輸入異或門) |
| 中文描述： | 四2輸入異或門（四2輸入異或門） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 103K |
| 代理商： | 74LV86 |
Philips Semiconductors
Product specification
74LV86
Quad 2-input EXCLUSIVE-OR gate
2
1998 Apr 20
853–1892 19255
FEATURES
Wide Operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Output capability: standard
I
CC
category: SSI
DESCRIPTION
The 74LV86 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT86.
The 74LV86 provides the 2-input EXCLUSIVE-OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nA, nB to nY
C
L
= 15 pF;
V
CC
= 3.3 V
11
ns
C
I
C
PD
Input capacitance
3.5
pF
Power dissipation capacitance per gate
V
I
= GND to V
CC1
30
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV86 N
74LV86 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV86 D
74LV86 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV86 DB
74LV86 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV86 PW
74LV86PW DH
SOT402-1
PIN CONFIGURATION
SV00481
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
LOGIC SYMBOL (IEEE/IEC)
SV00479
1
4
9
12
2
5
10
13
3
6
8
11
= 1
= 1
= 1
= 1
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