參數(shù)資料
型號(hào): 74LV74PW,112
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,400
系列: 74LV
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類(lèi)型: D 型
輸出類(lèi)型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 56MHz
觸發(fā)器類(lèi)型: 正邊沿
輸出電流高,低: 12mA,12mA
電源電壓: 1 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
74LV74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 9 September 2013
4 of 19
NXP Semiconductors
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
5.
Pinning information
5.1 Pinning
5.2 Pin description
Fig 5.
Pin configuration (DIP16, SO16 and (T)SSOP16)
1SD
74LV74
1RD
VCC
1D
2RD
1CP
2D
2CP
1Q
2SD
1Q
2Q
GND
2Q
aaa-008835
1
2
3
4
5
6
7
8
10
9
12
11
14
13
Table 2.
Pin description
Symbol
Pin
Description
1RD
1
asynchronous reset-direct input (active-LOW)
1D
2
data inputs
1CP
3
clock input (LOW-to-HIGH), edge-triggered)
1SD
4
asynchronous set-direct input (active-LOW)
1Q
5
true flip-flop outputs
1Q
6
complement flip-flop outputs
GND
7
ground (0 V)
2Q
8
complement flip-flop outputs
2Q
9
true flip-flop outputs
2SD
10
asynchronous set-direct input (active-LOW)
2CP
11
clock input (LOW-to-HIGH), edge-triggered)
2D
12
data inputs
2RD
13
asynchronous reset-direct input (active-LOW)
VCC
14
supply voltage
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