參數(shù)資料
型號(hào): 74LV74
廠商: NXP Semiconductors N.V.
英文描述: Dual D-type flip-flop with set and reset;positive-edge trigger(上升沿觸發(fā),帶置位和復(fù)位的雙D觸發(fā)器)
中文描述: 雙D型觸發(fā)器設(shè)置和復(fù)位觸發(fā)器,積極邊緣觸發(fā)(上升沿觸發(fā),帶置位和復(fù)位的雙?觸發(fā)器)
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 125K
代理商: 74LV74
Philips Semiconductors
Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
2
1998 Apr 20
853-1888 19258
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Output capability: standard
I
CC
category: flip-flops
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
C
L
= 15pF
V
CC
= 3.3V
11
14
14
ns
f
max
Maximum clock frequency
C
L
= 15pF
V
CC
= 3.3V
76
MHz
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
Input capacitance
Power dissipation capacitance per flip-flop
3.5
24
pF
pF
Notes 1 and 2
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
74LV74 N
74LV74 N
SOT27-1
14-Pin Plastic SO
74LV74 D
74LV74 D
SOT108-1
14-Pin Plastic SSOP Type II
74LV74 DB
74LV74 DB
SOT337-1
14-Pin Plastic TSSOP Type I
74LV74 PW
74LV74PW DH
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 13
1R
D,
2R
D
Asynchronous reset-direct input
(active-LOW)
2, 12
1D, 2D
Data inputs
3, 11
1CP, 2CP
Clock input (LOW-to-HIGH),
edge-triggered)
4, 10
1S
D,
2S
D
Asynchronous set-direct input
(active-LOW)
5, 9
1Q, 2Q
True flip-flop outputs
6, 8
1Q
,
2Q
GND
Complement flip-flop outputs
7
Ground (0V)
14
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
R
D
H
L
L
OUTPUTS
Q
H
L
H
S
D
L
H
L
CP
X
X
X
D
X
X
X
Q
L
H
H
INPUTS
R
D
H
H
OUTPUTS
Q
n+1
L
H
S
D
H
H
CP
D
L
H
Q
n+1
H
L
H
L
X
=
=
=
=
HIGH voltage level
LOW voltage level
don’t care
LOW-to-HIGH CP transition
state after the next LOW-to-HIGH CP transition
Q
n+1
=
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