參數(shù)資料
型號(hào)： 74LV4316PW-T
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 多路復(fù)用及模擬開(kāi)關(guān)
英文描述： QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 156K
代理商： 74LV4316PW-T
Philips Semiconductors
Product specification
74LV4316
Quad bilateral switches
2
1998 Jun 23
853-2079 19619
FEATURES
Optimized for Low Voltage applications: 1.0V to 6.0V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Low typ “ON” resistance:
80
W at VCC – VEE = 4.5V
120
W at VCC – VEE = 3.0V
295
W at VCC – VEE = 2.0V
Logic level translation: to enable 3V logic to communicate
with
"3V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC category: MSI
DESCRIPTION
The 74LV4316 is a low-voltage CMOS device that is pin and
function compatible with 74HC/HCT4316.
The 74LV4316 has four independent analog switches. Each switch
has two input/output terminals (nY, nZ) and an active HIGH select
input (nS). When the enable input (E) is HIGH, all four analog
switches are turned off.
Current through a switch will not cause additional VCC current provided
the voltage at the terminals of the switch is maintained within the
supply voltage range; VCC > (VY, VZ) > VEE. Inputs nY and nZ are
electrically equivalent terminals. VCC and GND are the supply voltage
pins for the digital control inputs (E and nS). The VCC to GND ranges
are 1.0 to 6.0 V.
The analog inputs/outputs (nY and nZ) can swing between VCC as a
positive limit and VEE as a negative limit.
VCC – VEE may not exceed 6.0 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf v 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZH/tPZL
Turn “ON” time:
E to VOS
nS to VOS
CL = 15pF
RL = 1KW
VCC= 3.3V
19
ns
tPHZ/tPLZ
Turn “OFF” time:
E to VOS
nS to VOS
20
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per switch
Notes 1, 2
13
pF
CS
Maximum switch capacitance
5
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
VCC = supply voltage in V:
(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV4316 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV4316 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV4316 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV4316 PW
74LV4316PW DH
SOT403-1
PIN CONFIGURATION
SV01650
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
VCC
1Z
1Y
2Y
2Z
2S
3S
E
1S
4S
4Z
4Y
3Y
3Z
VEE
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 4, 10, 13
1Z – 4Z
Independent inputs/outputs
2, 3, 11, 12
1Y – 4Y
Independent inputs/outputs
7
E
Enable input (active LOW)
8
GND
Ground (0V)
9
VEE
Negative supply voltage
15, 5, 6, 14
1S – 4S
Select inputs (active HIGH)
16
VCC
Positive supply voltage
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