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參數(shù)資料
| 型號： | 74LV4060PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 0K |
| 描述： | IC 14STAGE BINARY RIPPLE 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 74LV |
| 邏輯類型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 14 |
| 復(fù)位： | 異步 |
| 計(jì)數(shù)速率： | 90MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 1 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
9397 750 14402
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 12 January 2005
7 of 21
Philips Semiconductors
74LVT16652A
3.3 V 16-bit bus transceiver/register; 3-state
7.
Functional description
7.1 Function table
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
[2]
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
[3]
If both select controls (nSAB and nSBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must
be staggered in order to load both registers.
VCC
50
supply voltage
1B1
51
data input or output (B-side)
1B0
52
data input or output (B-side)
GND
53
ground (0 V)
1SBA
54
B to A select input
1CPBA
55
B to A clock input
1OEBA
56
B to A output enable input
Table 3:
Pin description …continued
Symbol
Pin
Description
Table 4:
Function table [1]
Operating mode
Input
Data I/O
nOEAB
nOEBA
nCPAB
nCPBA
nSAB
nSBA
nAx
nBx
Isolation
L
H
H or L
X
input
Store A and B data
L
H
↑↑
X
input
Store A, hold B
X
H
↑
H or L
X
input
unspecied
Store A in both registers
H
↑↑
X
input
unspecied
Hold A, store B
L
X
H or L
↑
X
unspecied
input
Store B in both registers
L
↑↑
X
unspecied
input
Real-time B data to A bus
L
XXXL
output
input
Store B data to A bus
L
X
H or L
X
H
output
input
Real-time A data to B bus
H
X
L
X
input
output
Store A data to B bus
H
H or L
X
H
X
input
output
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H
output
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