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參數(shù)資料
| 型號： | 74LV4060D,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER 14STAGE BINARY 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | 74LV |
| 邏輯類型： | 二進(jìn)制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 14 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 90MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 1 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 838 (CN2011-ZH PDF) |
| 其它名稱： | 568-1572-5 74LV4060D 935066190112 |
9397 750 14402
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 12 January 2005
11 of 21
Philips Semiconductors
74LVT16652A
3.3 V 16-bit bus transceiver/register; 3-state
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2]
For valid test results, data must not be loaded into the ip-ops (or latches) after applying power.
[3]
Unused pins at VCC or GND.
[4]
This is the bus-hold overdrive current required to force the input to the opposite logic state.
[5]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC =1.2 VtoVCC = 3.3 V ± 0.3 V
a transition time of 100
s is permitted. This parameter is valid for Tamb = 25 °C only.
[6]
ICC is measured with 16 outputs LOW.
[7]
ICC is measured with outputs pulled to VCC or GND.
[8]
This is the increase in supply current for each input at the specied voltage level other than VCC or GND.
11. Dynamic characteristics
I
CC
additional supply current
per input pin
VCC = 3.3 V ± 0.3 V; one input at
VCC 0.6 V; other inputs at VCC
or GND
[8] -
0.1
0.2
mA
CI
input capacitance control
pins
VI = 0 V or 3.0 V
-
3
-
pF
CI/O
I/O pin capacitance
outputs disabled; VI = 0 V or
3.0 V
-9
-pF
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 8:
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum clock frequency
VCC = 2.7 V or 3.3 V ± 0.3 V;
see Figure 6
150
180
-
MHz
tPLH
propagation delay
nAx to nBx or nBx to nAx
see Figure 7
VCC = 3.3 V ± 0.3 V
0.5
2.1
3.4
ns
VCC = 2.7 V
-
3.9
ns
propagation delay
nCPAB to nBx or
nCPBA to nAx
see Figure 6
VCC = 3.3 V ± 0.3 V
1.5
2.5
4.2
ns
VCC = 2.7 V
-
4.7
ns
propagation delay
nSAB to nBx or
nSBA to nAx
see Figure 8
VCC = 3.3 V ± 0.3 V
1.0
2.3
4.5
ns
VCC = 2.7 V
-
5.4
ns
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