參數(shù)資料
型號(hào): 74LV4020DB,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 3/10頁(yè)
文件大小: 0K
描述: IC 14BIT BINARY RIPPLE 16-SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 78
系列: 74LV
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 14
復(fù)位: 異步
計(jì)數(shù)速率: 100MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 1 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
其它名稱: 568-2970-5
935202710112
74LV4020_1
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
2 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
4.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
5.
Ordering information
Table 1:
Quick reference data
GND = 0 V; Tamb =25 °C; tr =tf = 2.5 ns.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tPHL,
tPLH
propagation delay
CL = 15 pF; VCC = 3.3 V
CP to Q0
-
12
-
ns
Qn to Q(n+1)
-
7
-
ns
tPHL
propagation delay
CL = 15 pF; VCC = 3.3 V
MR to Qn
-
16
-
ns
fmax
maximum input clock
frequency
CL = 15 pF; VCC = 3.3 V
-
100
-
MHz
Ci
input capacitance
-
3.5
-
pF
CPD
power dissipation
capacitance
per gate; VI = GND to
VCC
[1] -20
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV4020N
40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74LV4020D
40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LV4020DB
40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV4020PW
40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
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