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參數(shù)資料
| 型號： | 74LV373 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | OCTAL D-TYPE TRANSPARENT LATCH(3-State) |
| 中文描述： | 八路D型透明鎖存器（3態(tài)） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 74LV373 |
Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
2
1998 Jun 10
853–1934 19545
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce) < 0.8V at V
CC
= 3.3V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2V at V
CC
= 3.3V,
T
amb
= 25
°
C
Common 3-State output enable input
Output capability: bus driver
I
CC
category: MSI
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
D
to Q
n
LE to Q
n
Input capacitance
C
L
= 15pF
V
CC
= 3.3V
10
12
ns
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
3.5
pF
Power dissipation capacitance per latch
Notes 1, 2
22
pF
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
74LV373 N
74LV373 N
SOT146-1
20-Pin Plastic SO
74LV373 D
74LV373 D
SOT163-1
20-Pin Plastic SSOP Type II
74LV373 DB
74LV373 DB
SOT339-1
20-Pin Plastic TSSOP Type I
74LV373 PW
74LV373PW DH
SOT360-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10
Q
0
–Q
7
3-State latch outputs
D
0
–D
7
Data inputs
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
V
CC
Positive supply voltage
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV373ATELL-E | 制造商:Renesas Electronics 功能描述:Cut Tape 制造商:Renesas 功能描述:Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R |
| 74LV373D | 功能描述:閉鎖 3.3V D-TYPE TRANS LATCH 3-S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LV373D,112 | 功能描述:閉鎖 3.3V D-TYPE TRANS RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LV373D,118 | 功能描述:閉鎖 3.3V D-TYPE TRANS RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LV373D118 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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