- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360487 > 74LV27PW (NXP SEMICONDUCTORS) Triple 3-input NOR gate PDF資料下載
參數(shù)資料
| 型號： | 74LV27PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple 3-input NOR gate |
| 中文描述： | LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NOR GATE, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 114K |
| 代理商： | 74LV27PW |
Philips Semiconductors
Product specification
74LV27
Triple 3-input NOR gate
2
1998 Apr 20
853–1896 19258
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C.
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C.
Output capability: standard
I
CC
category: SSI
DESCRIPTION
The 74LV27 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT27.
The 74LV27 provides the 3-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nA, nB, nC to nY
C
L
= 15 pF;
V
CC
= 3.3 V
8
ns
C
I
C
PD
Input capacitance
3.5
pF
Power dissipation capacitance per gate
See Notes 1 and 2
24
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV27 N
74LV27 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV27 D
74LV27 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV27 DB
74LV27 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV27 PW
74LV27PW DH
SOT402-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 3, 9
1A – 3A
Data inputs
2, 4, 10
1B – 3B
Data inputs
13, 5, 11
1C – 3C
Data inputs
7
GND
Ground (0 V)
12, 6, 8
1Y – 3Y
Data outputs
14
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
nA
nB
nC
nY
L
L
L
H
X
X
H
L
X
H
X
L
H
X
X
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV27PWDH | Triple 3-input NOR gate |
| 74LV27N | Triple 3-input NOR gate |
| 74LV30D | 2K, 256 X 8 SERIAL EE, 1.8V IND, -40C to +85C, 8-TSSOP, TUBE |
| 74LV30DB | 2K, 256 X8 SERIAL EE, 1.8V, -40C to +85C, 8-DFN, T/R |
| 74LV30N | Single 8-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV27PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-input NOR gate |
| 74LV27PW-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Triple 3-input NOR Gate |
| 74LV2G126AUSE-E | 制造商:Renesas Electronics Corporation 功能描述:Cut Tape |
| 74LV2G14AUSE-E | 制造商:Renesas Electronics 功能描述:Cut Tape 制造商:Renesas 功能描述:Inverter Schmitt Trigger 3-Element CMOS 8-Pin SSOP T/R |
| 74LV2G34AUSE-E | 制造商:Renesas Electronics Corporation 功能描述:Buffer 3-CH Non-Inverting CMOS 8-Pin SSOP T/R Cut Tape |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。