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參數(shù)資料
| 型號(hào)： | 74LV257D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quad 2-input multiplexer 3-State |
| 中文描述： | LV/LV-A/LVX/H SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | 74LV257D |
Philips Semiconductors
Product specification
74LV257
Quad 2-input multiplexer (3-State)
2
1998 May 20
853-1985 19420
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Non-inverting data path
Output capability: bus driver
I
CC
category: MSI
DESCRIPTION
The 74LV257 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT257.
The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which
select 4 bits of data from two sources and are controlled by a common
data select input (S). The data inputs from source 0 (1l
0
to 4l
0
) are
selected when input S is LOW and the data inputs from source 1 (1l
1
to 4l
1
) are selected when S in HIGH. Data appears at the outputs (1Y
to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is
the logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determined by the logic levels applied to S.
The outputs are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE
×
(1l
1
×
S + 1l
0
×
S)
2Y = OE
×
(2l
1
×
S + 2l
0
×
S)
3Y = OE
×
(3l
1
×
S + 3l
0
×
S)
4Y = OE
×
(4l
1
×
S + 4l
0
×
S)
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nl
0
, nl
1
to nY
S to nY
C
L
= 15 pF;
V
CC
= 3.3 V
10
14
3.5
ns
C
I
C
PD
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
Input capacitance
pF
Power dissipation capacitance per gate
V
I
= GND to V
CC1
30
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
74LV257 N
74LV257 N
SOT38-4
16-Pin Plastic SO
74LV257 D
74LV257 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV257 DB
74LV257 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV257 PW
74LV257PW DH
SOT403-1
PIN CONFIGURATION
SV00636
1
2
3
4
5
6
S
1I
0
1I
1
IY
2l
0
2l
1
V
CC
OE
4l
0
16
15
14
13
12
11
7
8
GND
3l
1
3Y
10
9
2Y
4l
1
4Y
3l
0
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
S
Common data select input
2, 5, 11, 14
1l
0
to 4l
0
1l
1
to 4l
1
1Y to 4Y
Data inputs from source 0
3, 6, 10, 13
Data inputs from source 1
4, 7, 9, 12
3-state multiplexer outputs
8
GND
Ground (0 V)
15
OE
3-State output enable input
(active LOW)
16
V
CC
Positive supply voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV257N | Quad 2-input multiplexer 3-State |
| 74LV257PW | Quad 2-input multiplexer 3-State |
| 74LV257PWDH | Quad 2-input multiplexer 3-State |
| 74LV257DB | Quad 2-input multiplexer 3-State |
| 74LV259 | 8-bit addressable latch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV257DB | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Quad 2-input multiplexer 3-State |
| 74LV257DB-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:2-Input Digital Multiplexer |
| 74LV257D-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:2-Input Digital Multiplexer |
| 74LV257N | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Quad 2-input multiplexer 3-State |
| 74LV257PW | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Quad 2-input multiplexer 3-State |
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