參數資料
型號: 74LV240DB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal buffer/line driver; inverting 3-State
中文描述: LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
文件頁數: 2/12頁
文件大?。?/td> 115K
代理商: 74LV240DB
Philips Semiconductors
Product specification
74LV240
Octal buffer/line driver; inverting (3-State)
2
1998 May 20
853–1923 19422
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Output capability: bus driver
I
CC
category: MSI
DESCRIPTION
The 74LV240 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT240.
The 74LV240 is an octal inverting buffer/line driver with 3-State
outputs. The 3-State outputs are controlled by the output enable
inputs 1OE and 2OE. A HIGH on nOE causes the outputs to
assume a high impedance OFF-state. The 74LV240 is identical to
the 74LV244 but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
1A
n
to 1Y
n
;
2A
n
to 2Y
n
Input capacitance
C
L
= 15 pF;
V
CC
= 3.3 V
9.0
ns
C
I
3.5
pF
C
PD
Power dissipation capacitance per buffer
V
CC
= 3.3 V
V
I
= GND to V
CC1
30
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°
C to +125
°
C
74LV240 N
74LV240 N
SOT146-1
20-Pin Plastic SO
–40
°
C to +125
°
C
74LV240 D
74LV240 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV240 DB
74LV240 DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV240 PW
74LV240PW DH
SOT360-1
PIN CONFIGURATION
SV00607
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A
0
2Y
0
1A
1
2Y
1
1A
2
2Y
2
1A
3
2Y
3
GND
2A
3
1Y
3
2A
2
1Y
2
2A
1
1Y
1
2A
0
1Y
0
2OE
V
CC
LOGIC SYMBOL
SV00608
1A0
2A0
2
17
1A1
2A1
4
15
1A2
2A2
6
13
1A3
2A3
8
11
1OE
2OE
1
19
1Y0
2Y0
18
3
1Y1
2Y1
16
5
1Y2
2Y2
14
7
1Y3
2Y3
12
9
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相關代理商/技術參數
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