參數(shù)資料
型號(hào)： 74LV165
廠商： NXP Semiconductors N.V.
英文描述： 8-bit parallel-in/serial-out shift register(8位并入串出移位寄存器)
中文描述： 8位parallel-in/serial-out移位寄存器（8位并入串出移位寄存器）
文件頁數(shù)： 2/14頁
文件大小： 137K
代理商： 74LV165
Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
2
1998 May 07
853–1915 19349
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT165.
The 74LV165 is an 8-bit parallel-load or serial-in shift register with
complementary serial outputs (Q
7
and Q
7
) available from the last
stage. When the parallel load (PL) input is LOW, parallel data from the
D
0
to D
7
inputs are loaded into the register asynchronously. When PL
is HIGH, data enters the register serially at the D
S
input and shifts one
place to the right (Q
0
→
Q
1
→
Q
2
, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter expansion by
tying the Q
7
output to the D
S
input of the succeeding stage.
The clock input is a gated-OR structure which allows one input to be
used as an active LOW clock enable (CE) input. The pin assignment
for the CP and CE inputs is arbitrary and can be reversed for layout
convenience. The LOW-to-HIGH transition of input CE should only
take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL is activated.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
Propagation delay
CE, CP to Q
7
, Q
7
PL to Q
7
, Q
7
D
7
to Q
7
, Q
7
f
max
Maximum clock frequency
C
I
Input capacitance
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
L
= 15 pF;
V
CC
= 3.3 V
18
18
14
ns
78
MHz
3.5
pF
C
PD
Power dissipation capacitance per gate
V
CC
= 3.3 V
V
I
CC1
35
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
74LV165 N
74LV165 N
SOT38-4
16-Pin Plastic SO
74LV165 D
74LV165 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV165 DB
74LV165 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV165 PW
74LV165PW DH
SOT403-1
PIN CONFIGURATION
SV00585
1
2
3
4
5
6
PL
CP
D
4
D
5
D
6
D
7
VCC
CE
D
3
16
15
14
13
12
11
7
8
GND
D
S
Q
7
10
9
Q
7
D
2
D
1
D
0
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
PL
Asynchronous parallel load
input (active LOW)
Clock input (LOW to
HIGH, edge-triggered)
Complementary output from
the last stage
Ground (0 V)
2
CP
7
Q
7
8
GND
9
Q
7
D
S
D
0
to D
7
Serial output from last stage
10
Serial data input
11, 12, 13, 14, 3, 4, 5, 6
Parallel data inputs
15
CE
Clock enable input
(active LOW)
Positive supply voltage
16
V
CC
相關(guān)PDF資料
PDF描述
74LV174 Hex D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的六D觸發(fā)器)
74LV174PWDH Hex D-type flip-flop with reset; positive-edge trigger
74LV175 Quad D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的四D觸發(fā)器)
74LV20PW Dual 4-input NAND gate
74LV20PWDH Sensors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74LV165A 制造商:TI 制造商全稱:Texas Instruments 功能描述:PARALLEL-LOAD 8-BIT SHIFT REGISTERS
74LV165AD 功能描述:計(jì)數(shù)器移位寄存器 8-BIT PAR IN/SER OUT SHIFT REG RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
74LV165AD,112 功能描述:計(jì)數(shù)器移位寄存器 8-BIT PAR IN/SER RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
74LV165AD,118 功能描述:計(jì)數(shù)器移位寄存器 8-BIT PAR IN/SER RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
74LV165AD-Q100J 制造商:NXP Semiconductors 功能描述:2500 制造商:NXP Semiconductors 功能描述:74LV165AD-Q100/SO16/REEL13// - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC SHIFT REGISTER 8BIT 16SOIC 制造商:NXP Semiconductors 功能描述:Counter Shift Registers 8bit serial-in parallel-out
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*