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參數(shù)資料
| 型號： | 74LV161DB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 中文描述： | LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-338, SSOP2-16 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 148K |
| 代理商： | 74LV161DB |
Philips Semiconductors
Presettable synchronous 4-bit binary counter;
asynchronous reset
Product specification
74LV161
1997 May 15
9
AC ELECTRICAL CHARACTERISTICS
(Continued)
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
–35
–12
–9
–7
2
40
58
70
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
h
Hold time
PE CEP CET to
D
n
, PE, CEP, CET to
CP
Figures 4 – 6
0
0
0
14
19
24
0
0
0
12
16
20
ns
Maximum clock
pulse frequency
f
max
Figures 1, 6
MHz
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V;
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Q
n
, TC
OUTPUT
t
W
SV00576
V
M
CP INPUT
V
M
t
PLH
t
PHL
1/f
max
V
OL
V
OH
GND
V
I
Figure 1. Clock (CP) to outputs (Q
n
, TC) propagation delays,
the clock pulse width and the maximum clock frequency.
t
rem
SV00577
V
M
MR INPUT
CP INPUT
V
I
V
I
GND
GND
V
OL
V
OH
Q
n
, TC
OUTPUT
V
M
V
M
t
PHL
t
W
Figure 2. Master reset (MR) pulse width,
the master reset to output (Q
n
, TC) propagation delays
and the master reset to clock (CP) removal times.
SV00578
V
M
CET INPUT
TC OUTPUT
V
M
t
PHL
t
PLH
GND
V
I
V
OL
V
OH
Figure 3. Input (CET) to output (TC) propagation delays.
SV00579
V
M
V
M
PE INPUT
CP INPUT
D
n
INPUT
V
M
t
h
t
su
t
su
t
su
t
su
t
h
t
h
t
h
GND
GND
GND
V
I
V
I
V
I
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 4. Set-up and hold times for input (D
n
)
and parallel enable input (PE).
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| 74LV161 | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LV161D | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LV161N | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LV161PW | Presettable synchronous 4-bit binary counter; asynchronous reset |
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相關代理商/技術參數(shù) |
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|---|---|
| 74LV161DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| 74LV161D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| 74LV161N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LV161PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LV161PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; asynchronous reset |
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