參數(shù)資料
型號: 74LV138PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 3-to-8 line decoder/multiplexer; inverting
中文描述: LV/LV-A/LVX/H SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
文件頁數(shù): 2/12頁
文件大?。?/td> 116K
代理商: 74LV138PWDH
Philips Semiconductors
Product specification
74LV138
3-to-8 line decoder/demultiplexer; inverting
2
1998 Apr 28
853–1903 19290
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT138.
The 74LV138 accepts three binary weighted address inputs (A
0
, A
1
,
A
2
) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y
0
to Y
7
).
The 74LV138 features three enable inputs: two active LOW (E
1
, and
E
2
) and one active HIGH (E
3
). Every output will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138 to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138 ICs and one inverter. The 74LV138 can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state. The 74LV138 is identical to the 74LV238
but has non-inverting (true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn,
E3 to Yn, En to Yn
C
L
= 15 pF;
V
CC
= 3.3 V
12
14
ns
ns
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per
package
V
CC
= 3.3 V
V
I
= GND to V
CC1
45
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
74LV138 N
74LV138 N
SOT38-4
16-Pin Plastic SO
74LV138 D
74LV138 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV138 DB
74LV138 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV138 PW
74LV138PW DH
SOT403-1
PIN CONFIGURATION
SV00524
1
2
3
4
5
6
7
A
0
A
1
A
2
E
1
E
2
E
3
Y
7
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
14
13
12
11
10
9
GND
Y
6
8
16
15
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 3
A
0
to A
2
E
1
to E
2
E
3
Address inputs
4, 5
Enable inputs (active LOW)
6
Enable inputs (active HIGH)
15, 14, 13, 12,
11, 10, 9, 7
Y
0 to
Y
7
Outputs
8
GND
Ground (0 V)
16
V
CC
Positive supply voltage
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