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參數(shù)資料
| 型號： | 74LV03PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | BREAKOUT TEST CABLE ASSEMBLY; BNC MALE TO INSULATED SPADE LUGS; APPROX. 6" LONG RED & BLACK LEADS |
| 中文描述： | LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 119K |
| 代理商： | 74LV03PW |
Philips Semiconductors
Product specification
74LV03
Quad 2-input NAND gate
1998 Apr 20
6
AC CHARACTERISTICS FOR 74LV03
GND = 0V; t
r
= t
f
≤
2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
1
50
17
13
10
2
–
3
LIMITS
–40 to +125
°
C
MIN
–
–
–
–
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
MIN
–
–
–
–
–
MAX
–
26
19
16
13
MAX
–
31
23
19
16
Propagation delay
nA, nB, to nY
t
PZL/
t
PLZ
Figures, 1, 2
ns
NOTE:
1
Unless otherwise stated, all typical values are at T
amb
= 25
°
C.
2
Typical value measured at V
CC
= 3.3V.
3
Typical value measured at V
CC
= 5.0V.
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5V * V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V and
V
X
= V
OL
+ 0.1 * V
CC
at V
CC
2.7V and
2.7V
3.6V
2.7V and
4.5V
3.6V
4.5V
V
I
nA, nB INPUT
GND
V
CC
nY OUTPUT
V
OL
V
X
t
PZL
t
PLZ
V
M
V
M
SV00358
Figure 1. Input (nA, nB) to output (nY) propagation delays.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance.
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2.7V
2.7–3.6V
4.5V
V
CC
50 pF
SV00896
S
1
t
PLZ/
t
PZL
t
PHZ/
t
PZH
Open
2 * V
CC
GND
R
L
= 1k
Open
GND
2 * V
CC
Figure 2. Load circuitry for switching times
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相關(guān)代理商/技術(shù)參數(shù) |
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| 74LV03PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad 2-input NAND gate |
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| 74LV0451D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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