參數(shù)資料
型號(hào): 74LCXR2245WMX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCVR BIDIRECT LV 20SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74LCX
邏輯類型: 收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 12mA,12mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1211 (CN2011-ZH PDF)
其它名稱: 74LCXR2245WMXDKR
10
COMMERCIALTEMPERATURERANGE
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 7.
Name(1)
Description
OFn2, OFn1, OFn0
These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to
(Offset Bits 2, 1 & 0)
start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the
F0i input of the device. See Figure 5.
DLEn
(Data Latch Edge)
ST-BUS mode:
DLEn = 0, if clock rising edge is at the point of the bit cell.
DLEn = 1, if when clock falling edge is at the of the bit cell.
GCI mode:
DLEn = 0, if clock falling edge is at the point of the bit cell.
DLEn = 1, if when clock rising edge is at the of the bit cell.
Read/Write Address:
03H for FOR0 register,
04H for FOR1 register.
Reset Value:
0000H for all FOR registers.
15
14
13
12
11
10
9876543210
OF32
OF31
OF30
DLE3
OF22
OF21
OF20
DLE2
OF12
OF11
OF10
DLE1
OF02
OF01
OF00
DLE0
FOR0 Register
15
14
13
12
11
10
9876543210
OF72
OF71
OF70
DLE7
OF62
OF61
OF60
DLE6
OF52
OF51
OF50
DLE5
OF42
OF41
OF40
DLE4
FOR1 Register
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