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參數(shù)資料
| 型號： | 74LCXH162244MEX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFF DVR 16BIT LOW V 48SSOP |
| 產(chǎn)品變化通告： | Die Material/Mold Compound Change 10/Sept/2008 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 74LCXH |
| 邏輯類型： | 緩沖器/線路驅(qū)動器，非反相 |
| 元件數(shù)： | 4 |
| 每個元件的位元數(shù)： | 4 |
| 輸出電流高，低： | 12mA，12mA |
| 電源電壓： | 2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
5
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
In ST-BUS mode, the falling edge of the frame measurement signal (FE)
isevaluatedagainstthefallingedgeoftheST-BUS framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 7 and Figure 4 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
TheIDT72V70180providesuserswiththecapabilityofinitializingtheentire
connectionmemoryblockintwoframes.Tosetbits11to15ofeveryconnection
memorylocation,firstprogramthedesiredpatterninbits5to9oftheIMSregister.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT72V70180
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesontheper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C bit of the connection memory.
VARIABLE DELAY MODE (
V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70180 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifinput
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 1 shows the possible delays for the IDT72V70180 in the
variable delay mode.
CONSTANT DELAY MODE (
V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70180, the minimum throughput delay achievable in the constant
delaymodewillbeoneframe.Forexample,wheninputtime-slot31isswitched
tooutputtime-slot0.Themaximumdelayof94time-slotsofdelayoccurswhen
time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 2.
MICROPROCESSOR INTERFACE
The IDT72V70180 provides a parallel microprocessor interface for multi-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected to
the device. If the IM pin is high, the device monitors the AS/ALE and DS/
RD to
determine what mode the IDT72V70180 should operate in.
If DS/
RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/
RDishighattherisingedgeofAS/ALE,thenthemode
2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/
RD),Read/Write/Write(R/W/WR),
Chip select (
CS) and Data transfer acknowledge (DTA). See Figure 11 and
Figure 12 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(
CS, DS, R/Wand DTA).SeeFigure13and14 forMotorolanon-multiplexed
microporttiming.
The IDT72V70180 microport provides access to the internal registers,
connectionanddatamemories.Alllocationsprovideread/writeaccessexcept
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70180.
If the A7 address input is low, then A6 through A0 are used to address the
interfacemodeselection(IMS),control(CR),framealignment(FAR)andframe
input offset (FOR) registers (Table 4). If the A7 is high, A6 and A5 are low, then
A4 through A0 are used to select 32 locations corresponding to data rate of the
ST-BUS. The address input lines and the stream address bits (STA) of the
control register allow access to the entire data and connection memories. The
control and IMS registers together control all the major functions of the device,
see Figure 3.
As explained in the Serial Data Interface Timing and Switching Configura-
tionssections,aftersystempower-up,theIMSregistershouldbeprogrammed
immediatelytoestablishthedesiredswitchingconfiguration.
The data in the control register consists of the memory block programming
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
addressbitsselectinternalmemorysubsectionscorrespondingtoinputoroutput
serialstreams.
The data in the IMS register consists of block programming bits (BPD0-
BPD4),blockprogrammingenablebit(BPE),outputstandbybit(OSB)andstart
frameevaluationbit(SFE).Theblockprogrammingandtheblockprogramming
enablebitsallowsuserstoprogramtheentireconnectionmemory(seeMemory
BlockProgrammingsection).IftheODEpinislow,theOSBbitenables(ifhigh)
ordisables(iflow)allST-BUSoutputdrivers.IftheODEpinishigh,thecontents
of the OSB bit is ignored and all TX output drivers are enabled.
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