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參數(shù)資料
| 型號： | 74LCX573MTC |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LATCH OCT D-TYPE 5V 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 系列： | 74LCX |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態(tài) |
| 電源電壓： | 2 V ~ 3.6 V |
| 獨立電路： | 1 |
| 延遲時間 - 傳輸： | 1.5ns |
| 輸出電流高，低： | 24mA，24mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1211 (CN2011-ZH PDF) |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX573 Rev. 1.6.1
2
74LCX573
—
Lo
w
V
olta
g
e
Octal
Latc
h
with
5V
T
olerant
Inputs
and
Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Logic Symbol
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of
Latch Enable
Functional Description
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode but this does not
interfere with entering new data into the latches.
Pin Names
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Latch Outputs
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
O0
LE
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
LE
O0
VCC
120
2
3
4
5
6
7
8
9
10
11
19
18
17
16
15
14
13
12
OE
Inputs
Outputs
OE
LE
D
On
LH
H
LH
L
LL
X
O0
HX
X
Z
D0 D1 D2 D3 D4 D5 D6 D7
O0
OE
LE
O1 O2 O3 O4 O5 O6 O7
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
D0
O0
Q
LE
OE
D1
O1
D
Q
LE
D2
O2
D
Q
LE
D3
O3
D
Q
LE
D4
O4
D
Q
LE
D5
O5
D
Q
LE
D6
O6
D
Q
LE
D7
O7
D
Q
LE
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LCX573MTC | 制造商:Fairchild Semiconductor Corporation 功能描述:Latch Logic IC |
| 74LCX573MTC_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs |
| 74LCX573MTC_Q | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LCX573MTCX | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LCX573MTCX_NL | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs |
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