參數(shù)資料
型號(hào): 74LCX16841MTD
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC LATCH TRANSP 20BIT LV 56TSSOP
標(biāo)準(zhǔn)包裝: 34
系列: 74LCX
邏輯類型: D 型透明鎖存器
電路: 10:10
輸出類型: 三態(tài)
電源電壓: 2 V ~ 3.6 V
獨(dú)立電路: 2
延遲時(shí)間 - 傳輸: 1.5ns
輸出電流高,低: 24mA,24mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
www.fairchildsemi.com
2
74LCX16841
Connection Diagram
Truth Tables
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Functional Description
The LCX16841 contains twenty D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e. a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
LE1
OE1
D0–D9
O0–O9
XH
X
Z
HL
L
HL
H
LL
X
O0
Inputs
Outputs
LE2
OE2
D10–D19
O10–O19
XH
X
Z
HL
L
HL
H
LL
X
O0
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