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參數(shù)資料
| 型號： | 74LCX16500G |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs |
| 中文描述： | LVC/LCX/Z SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA54 |
| 封裝： | 5.50 MM, PLASTIC, MO-205, FBGA-54 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 101K |
| 代理商： | 74LCX16500G |
2002 Fairchild Semiconductor Corporation
DS012407
www.fairchildsemi.com
March 1995
Revised June 2002
7
74LCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
5V Tolerant Inputs and Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16500 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with the capability of interfacing to a 5V
signal environment.
The LCX16500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
I
5V tolerant inputs and outputs
I
2.3V–3.6V V
CC
specifications provided
I
6.0 ns t
PD
max (V
CC
=
3.3V), 20
μ
A I
CC
max
I
Power down high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
±
24 mA output drive (V
CC
=
3.0V)
I
Uses patented noise/EMI reduction circuitry
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2:
Ordering code
“
G
”
indicates Trays.
Note 3:
Devices also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Order Number
74LCX16500G
(Note 2)(Note 3)
74LCX16500MEA
(Note 3)
74LCX16500MTD
(Note 3)
Package Number
BGA54A
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74LCX16500GX | 功能描述:總線收發(fā)器 UB Transceiver LV 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MEA | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MEA_Q | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MEAX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MTD | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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