- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369308 > 74LCX16373TTR (意法半導(dǎo)體) LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH(3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTS PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LCX16373TTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH(3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTS |
| 中文描述： | 低電壓CMOS 16位D型鎖存器（3 -國家與承受5V的輸入和輸出） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 74LCX16373TTR |
74LCX16373
5/9
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value ofthe difference between the actual propagation delayfor anytwo outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
=
t
r
(ns)
-40 to 85
°
C
-55 to 125
°
C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time (Dn to Qn)
2.7
50
500
2.5
1.5
1.5
1.5
1.5
1.5
5.9
5.4
6.4
5.5
6.5
1.5
1.5
1.5
1.5
1.5
5.9
5.4
6.4
5.5
6.5
ns
3.0 to 3.6
2.7
3.0 to 3.6
2.7
t
PLH
t
PHL
Propagation Delay
Time (LE to Qn)
50
500
2.5
ns
t
PZL
t
PZH
Output Enable Time
to HIGH and LOW
level
Output Disable Time
from HIGH to LOW
level
Set-Up Time, HIGH
or LOW level
(Dn to LE)
Hold Time, HIGH or
LOW level
(Dn to LE)
LE Pulse Width,
HIGH
50
500
2.5
ns
3.0 to 3.6
1.5
6.1
1.5
6.1
t
PLZ
t
PHZ
2.7
50
500
2.5
1.5
6.3
1.5
6.3
ns
3.0 to 3.6
1.5
6.0
1.5
6.0
t
S
2.7
50
500
2.5
2.5
2.5
ns
3.0 to 3.6
2.5
2.5
t
h
2.7
50
500
2.5
1.5
1.5
ns
3.0 to 3.6
1.5
1.5
t
W
2.7
50
500
2.5
3.0
3.0
3.0
3.0
ns
3.0 to 3.6
3.0 to 3.6
t
OSLH
t
OSHL
Output ToOutput
Skew Time (note1,
2)
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
°
C
Min.
Typ.
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
3.3
V
IN
= 0 to V
CC
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
7
8
pF
pF
20
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LCX16373 | Low Voltage 16-Bit D-Type Latch 3-State with 5V Tolerant Inputs and Output(三態(tài)低電壓16位D觸發(fā)器) |
| 74LCX16374A | Low Voltage 16-Bit D-Type Flip Flop 3-State with 5V Tolerant Inputs and Outputs(三態(tài)低壓16位D觸發(fā)器) |
| 74LCX16374TTR | LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS |
| 74LCX16374 | Low Voltage 16-Bit D-Type Flip Flop 3-State with 5V Tolerant Inputs and Outputs(三態(tài)低電壓16位D觸發(fā)器) |
| 74LCX240 | LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE INV) WITH 5V TOLERANT INPUTS AND OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LCX16374 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs |
| 74LCX16374 WAF | 制造商:Texas Instruments 功能描述: |
| 74LCX16374AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit D-Type Flip-Flop |
| 74LCX16374G | 功能描述:觸發(fā)器 D-Type Flip Flop LV 16Bit 5V RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LCX16374GX | 功能描述:觸發(fā)器 D-Type Flip Flop LV 16Bit 5V RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。