參數(shù)資料
型號: 74LCX16373
廠商: 意法半導體
英文描述: Low Voltage 16-Bit D-Type Latch 3-State with 5V Tolerant Inputs and Output(三態(tài)低電壓16位D觸發(fā)器)
中文描述: 低電壓16位D類鎖存3與5V容限輸入和輸出(三態(tài)低電壓16位?觸發(fā)器國)
文件頁數(shù): 5/9頁
文件大?。?/td> 90K
代理商: 74LCX16373
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
T
A
= 25
o
C
Min.
Typ.
Unit
V
CC
(V)
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance (note 1)
3.3
3.3
3.3
V
IN
=0toV
CC
V
IN
=0toV
CC
f
IN
=10MHz
V
IN
=0or V
CC
7
8
20
pF
pF
pF
1) C
PD
isdefined as the value ofthe IC’s internalequivalent capacitance which iscalculated fromtheoperating currentconsumption without load. Average
operting current can beobtained bythe followingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+I
CC
/n(per circuit)
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 2.5 ns)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
Waveform
-40 to 85
o
C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
1.5
1.5
3.0
3.0
Max.
5.9
5.4
6.4
5.5
6.5
6.1
6.3
6.0
t
PLH
t
PHL
Propagation Delay Time Dn to Qn
2.7
1
ns
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
3.0to3.6
t
PLH
t
PHL
Propagation Delay Time LE to Qn
1
ns
t
PZL
t
PZH
Output Enable Time to HIGH and LOW
level
2
ns
t
PLZ
t
PHZ
Output Disable Time from HIGh and
LOW level
2
ns
t
s
Setup Time, HIGh or LOW level Dn to
LE
1
ns
t
h
Hold Time, HIGh or LOW level Dn to LE
1
ns
t
w
LE Pulse Width, HIGH or LOW
3
ns
t
OSLZ
t
OSHL
Output to Output Skew Time (note 1, 2)
1.0
ns
1) Skew isdefined as the absolute value of the difference between theactual propagation delay forany twooutputs ofthe samedevice switching in the
same direction, either HIGHor LOW (t
OSLH
=|t
PLHm
-t
PLHn
|,t
OSHL
=|t
PHLm
-t
pHLn
|)
2) Parameter guaranteed bydesign
74LCX16373
5/9
相關PDF資料
PDF描述
74LCX16374A Low Voltage 16-Bit D-Type Flip Flop 3-State with 5V Tolerant Inputs and Outputs(三態(tài)低壓16位D觸發(fā)器)
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