參數(shù)資料
型號(hào): 74LCX14SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 1/13頁
文件大?。?/td> 0K
描述: IC INVERTER HEX SCHMITT 14SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LCX
邏輯類型: 逆變器,緩沖器
電路數(shù): 6
輸入數(shù): 1
特點(diǎn): 施密特觸發(fā)器
電源電壓: 2 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 10µA
輸出電流高,低: 24mA,24mA
邏輯電平 - 低: 0.4 V ~ 0.6 V
邏輯電平 - 高: 1.7 V ~ 2.2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 6.5ns @ 3.3V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
74LCX14
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Inputs
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX14 Rev. 1.7.1
74LCX14
Low Voltage Hex Inverter with 5V Tolerant
Schmitt Trigger Inputs
Features
5V tolerant inputs
2.3V–3.6V VCC specifications provided
6.5ns tPD max. (VCC = 3.3V), 10A ICC max.
Power down high impedance inputs and outputs
±24mA output drive (VCC = 3.0V)
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
> 2000V
– Machine model
> 200V
Leadless DQFN package
General Description
The LCX14 contains six inverter gates each with a
Schmitt trigger input. They are capable of transforming
slowly changing input signals into sharply defined, jitter-
free output signals. In addition, they have a greater noise
margin than conventional inverters.
The LCX14 has hysteresis between the positive-going
and negative-going input thresholds (typically 1.0V)
which is determined internally by transistor ratios and is
essentially insensitive to temperature and supply voltage
variations.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74LCX14M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX14SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX14BQX(1)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX14MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Implements proprietary noise/EMI reduction circuitry
December 2013
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