參數(shù)資料
型號： 74LCX126SJX
廠商： Fairchild Semiconductor
文件頁數(shù)： 3/9頁
文件大?。?/td> 0K
描述： IC BUFFER QUAD LV N-INV 14SOP
標(biāo)準(zhǔn)包裝： 2,000
系列： 74LCX
邏輯類型： 緩沖器/線路驅(qū)動(dòng)器，非反相
元件數(shù)： 4
每個(gè)元件的位元數(shù)： 1
輸出電流高，低： 24mA，24mA
電源電壓： 2 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOIC
包裝： 帶卷 (TR)
BU1572GUW, BU1573KV, BU1574KU
Technical Note
3/12
www.rohm.com
2009.04- Rev.B
2009 ROHM Co., Ltd. All rights reserved.
●Terminal functions (BU1572GUW/BU1573KV)
PIN
No.
PIN
Name
Interface Type *1
In/Out
Active
Level
Init
Description
In/output
type
TYPE 1
TYPE 2
1
LCDVSI
In
*
-
Vertical timing input
C *1
2
N.C.*2
-
3
LCDHSI/
LCDRS01
*3
LCDHSI
In
*
-
Horizontal timing input/
Register select input signal 0
C *1
4
LCDCSBI/
SDA
LCDCSBI
SDA
In/Out
Low/
DATA
In
Chip select input signal /
In/output serial data
G
5
LCDWRDBI/
SDC
LCDWRBI
SDC
In
Low/
CLK
-
Write enable input signal /
In/output serial clock
D *1
6
LCDRDBI/
I2CDEV0
LCDRDBI
I2CDEV0
In
Low/ *
-
Read enable input signal /
I2C device address setting
D *1
7
LCDDI0
In/Out
DATA
In
Data input:
bit 0
H *1
8
LCDDI1
In/Out
DATA
In
Data input:
bit 1
H *1
9
LCDDI2
In/Out
DATA
In
Data input:
bit 2
H *1
10
LCDDI3
In/Out
DATA
In
Data input:
bit 3
H *1
11
LCDDI4
In/Out
DATA
In
Data input:
bit 4
H *1
12
LCDDI5
In/Out
DATA
In
Data input:
bit 5
H *1
13
LCDDI6
In/Out
DATA
In
Data input:
bit 6
H *1
14
LCDDI7
In/Out
DATA
In
Data input:
bit 7
H *1
15
LCDDI8
In/Out
DATA
In
Data input:
bit 8
H *1
16
LCDDI9
In/Out
DATA
In
Data input:
bit 9
H *1
17
LCDDI10
In/Out
DATA
In
Data input:
bit 10
H *1
18
LCDDI11
In/Out
DATA
In
Data input:
bit 11
H *1
19
LCDDI12
In/Out
DATA
In
Data input:
bit 12
H *1
20
LCDDI13
In/Out
DATA
In
Data input:
bit 13
H *1
21
LCDDI14
In/Out
DATA
In
Data input:
bit 14
H *1
22
LCDDI15
In/Out
DATA
In
Data input:
bit 15
H *1
23
LCDDI16
In/Out
DATA
In
Data input:
bit 16
H *1
24
LCDDI17
In/Out
DATA
In
Data input:
bit 17
H *1
25
ENAI
*3
ENAI
In
*
-
RAM write enable input signal
C *1
26
VLDI
*3
VLDI
In
*
-
VLD input signal
C *1
27
VDDIO
-
PWR
-
DIGITAL IO power source
-
28
DCKI
In
CLK
-
Clock input
D *1
29
GND
-
GND
-
Common GROUND
-
30
VDD
-
PWR
-
CORE power source
-
31
MSEL0/
LCDRS0I
MSEL0 *3
In
*
-
Mode select 0/
Register select input signal 0
A
32
MSEL1/
LCDRS1I
MSEL1 *3
In
*
-
Mode select 1/
Register select input signal 1
A
※Change by setup by the register is possible for the "*" display in the column of an Active level. Moreover, Init is a pin state under reset.
*1 : It suspends during reset (initial state)
*2 : With no ball(Please connect it with GND for BU1573KV)
*3 : Please connect with GND.
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