參數(shù)資料
型號(hào): 74LCX02SJX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 0K
描述: IC GATE NOR QUAD 2IN LV 14SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LCX
邏輯類型: 或非門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 10µA
輸出電流高,低: 24mA,24mA
邏輯電平 - 低: 0.7 V ~ 0.8 V
邏輯電平 - 高: 1.7 V ~ 2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 5.2ns @ 3.3V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
74LCX02
Lo
w
V
olta
g
e
Quad
2-Input
NOR
Gate
with
5V
T
olerant
Inputs
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX02 Rev. 1.6.0
January 2008
74LCX02
Low Voltage Quad 2-Input NOR Gate with 5V
Tolerant Inputs
Features
5V tolerant inputs
2.3V–3.6V VCC specifications provided
5.2ns tPD max. (VCC = 3.3V), 10A ICC max.
Power down high impedance inputs and outputs
±24mA output drive (VCC = 3.0V)
Latch-up performance exceeds 500mA
ESD performance:
– Human body model
> 2000V
– Machine model
> 200V
General Description
The LCX02 contains four 2-input NOR gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V
systems to 3V systems.
The 74LCX02 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Order Number
Package
Number
Package Description
74LCX02M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX02SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX02MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
An, Bn
Inputs
On
Outputs
Implements proprietary noise/EMI reduction circuitry
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