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參數(shù)資料
| 型號： | 74HCT73 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual JK flip-flop with reset;negative-edge trigger(帶復(fù)位的雙JK觸發(fā)器；下降沿觸發(fā)) |
| 中文描述： | 雙JK觸發(fā)器的復(fù)位觸發(fā)器，負(fù)邊沿觸發(fā)器（帶復(fù)位的雙JK觸發(fā)器;下降沿觸發(fā)） |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 52K |
| 代理商： | 74HCT73 |
December 1990
2
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
FEATURES
Output capability: standard
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT73 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT73 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
16
16
15
77
3.5
30
15
18
15
79
3.5
30
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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