參數(shù)資料
型號: 74HCT597
廠商: NXP Semiconductors N.V.
英文描述: 8-bit shift register with input flip-flops
中文描述: 8位輸入翻轉(zhuǎn)移位寄存器觸發(fā)器
文件頁數(shù): 2/12頁
文件大小: 84K
代理商: 74HCT597
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
FEATURES
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
SH
CP
to Q
ST
CP
to Q
PL to Q
maximum clock frequency SH
CP
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
17
25
21
96
3.5
29
20
29
26
83
3.5
32
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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