參數(shù)資料
型號(hào): 74HCT574
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SO -40 to 85
中文描述: 八路D型觸發(fā)器,上升沿觸發(fā),三態(tài)
文件頁數(shù): 5/7頁
文件大?。?/td> 57K
代理商: 74HCT574
December 1990
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74HC/HCT574
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
47
17
14
44
16
13
39
14
11
14
5
4
14
5
4
6
2
2
0
0
0
37
112
133
150
30
26
140
28
24
125
25
21
60
12
10
190
35
33
175
35
30
155
31
26
75
15
13
225
45
38
210
42
36
190
38
32
90
18
15
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output enable
time OE to Q
n
ns
Fig.7
t
PHZ
/ t
PLZ
3-state output disable
time OE to Q
n
ns
Fig.7
t
THL
/ t
TLH
output transition time
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
60
12
10
5
5
5
6.0
30
35
100
20
17
75
15
13
5
5
5
4.8
24
28
120
24
20
90
18
15
5
5
5
4.0
20
24
ns
Fig.6
t
su
set-up time
D
n
to CP
ns
Fig.8
t
h
hold time
D
n
to CP
ns
Fig.8
f
max
maximum clock pulse
frequency
MHz
Fig.6
相關(guān)PDF資料
PDF描述
74HC574 Octal D-type flip-flop; positive edge-trigger; 3-state
74HCT583 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-TSSOP -40 to 85
74HC583 4-bit full adder with fast carry
74HCT643 Dual 4-Input Positive-NAND Gates 14-SSOP -40 to 85
74HC643 Octal bus transceiver; 3-state; true/inverting
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