參數(shù)資料
型號: 74HCT573
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
中文描述: 八路D型透明鎖存器,三態(tài)
文件頁數(shù): 7/7頁
文件大小: 61K
代理商: 74HCT573
December 1990
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
AC WAVEFORMS
Fig.6
Waveforms showing the data input (D
n
) to
output (Q
n
) propagation delays and the
output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Q
n
) propagation delays and the
output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.8
Waveforms showing the 3-state enable and
disable times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9
Waveforms showing the data set-up and
hold times for D
n
input to LE input.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
相關PDF資料
PDF描述
74HC573 Octal D-type transparent latch; 3-state
74HCT573PW 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-PDIP -40 to 85
74HC573 Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)
74HCT574 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SO -40 to 85
74HC574 Octal D-type flip-flop; positive edge-trigger; 3-state
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