參數(shù)資料
型號(hào)： 74HCT563LC
英文描述： 8-Bit D-Type Latch
中文描述： 8位D型鎖存器
文件頁(yè)數(shù)： 2/13頁(yè)
文件大?。?/td> 80K
代理商： 74HCT563LC
1998 Sep 30
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74HC/HCT257
FEATURES
Non-inverting data path
3-state outputs interface directly with system bus
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT257 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT257 have four identical 2-input multiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The “257” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE.(1I
1
.S
+
1I
0
.S)
2Y = OE.(2I
1
.S
+
2I
0
.S)
3Y = OE.(3I
1
.S
+
3I
0
.S)
4Y = OE.(4I
1
.S
+
4I
0
.S)
The “257” is identical to the “258” but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nI
0
, nI
1
to nY
S to nY
input capacitance
power dissipation capacitance per multiplexer
C
L
= 15 pF; V
CC
= 5 V
11
14
3.5
45
13
17
3.5
45
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
相關(guān)PDF資料
PDF描述
74HCT73D IC-SM-74HCT CMOS
74HCT9046AD-T Analog Phase-Locked Loop
74HC257 Quad. 2-to-1-line Data Selectors/Multiplexers(with noninverted 3-state outputs)
74HC257 High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs
74HC257 QUAD 2-CHANEL MULTIPLEXER (3-STATE)
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