參數(shù)資料
型號(hào): 74HCT4094
廠商: NXP Semiconductors N.V.
英文描述: 8-stage shift-and-store bus register
中文描述: 8級(jí)移位并存儲(chǔ)總線寄存器
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 72K
代理商: 74HCT4094
December 1990
2
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
FEATURES
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP
0
to QP
7
). The parallel outputs
may be connected directly to common bus lines.
Data is shifted on the positive-going clock (CP) transitions.
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
1
and QS
2
) are available for
cascading a number of “4094” devices. Data is available at
QS
1
on the positive-going clock edges to allow high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS
2
on
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to QS
1
CP to QS
2
CP to QP
n
STR to QP
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
15
13
20
18
95
3.5
83
19
18
21
19
86
3.5
92
ns
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
相關(guān)PDF資料
PDF描述
74HC4094 8-stage shift-and-store bus register
74HC4094 8 BIT SIPO SHIFT LATCH REGISTER 3-STATE
74HC4094 High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State
74HC4094 8-BIT SHIFT AND STORE REGISTER (3-STAFE)
74HC4094 8-Bit Serial-Input Shift Register With Latched 3-State Outputs(High-Performance Silicon-Gate CMOS)
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