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參數(shù)資料
| 型號： | 74HCT4060N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 14STAGE BINARY RIPPLE 16DIP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | 74HCT |
| 邏輯類型： | 二進(jìn)制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 14 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 88MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-DIP |
| 包裝： | 管件 |
| 其它名稱： | 568-7853-5 74HCT4060N 74HCT4060N,652-ND 74HCT4060N-ND 933670400652 |
1.
General description
The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible
with the HEF4060.
The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators
with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and
Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator
conguration allows design of either RC or crystal oscillator circuits. The oscillator may be
replaced by an external clock signal at input RS. In this case keep the other oscillator pins
(RTC and CTC) oating. The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of
other input conditions. In the HCT version, the MR input is TTL compatible, but the RS
input has CMOS input switching levels and can be driven by a TTL output by using a
pull-up resistor to VCC.
2.
Features
I All active components on chip
I RC or crystal oscillator conguration
I Complies with JEDEC standard no. 7 A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specied from 40 °Cto+85 °C and from 40 °C to +125 °C
3.
Applications
I Control counters
I Timers
I Frequency dividers
I Time-delay circuits
74HC4060; 74HCT4060
14-stage binary ripple counter with oscillator
Rev. 03 — 14 July 2008
Product data sheet
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