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參數(shù)資料
| 型號： | 74HCT4059N3 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable divide-by-n counter |
| 中文描述： | HCT SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-222-1, MS-001AF, DIP-24 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 147K |
| 代理商： | 74HCT4059N3 |
1998 Jul 08
13
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
The arrangement shown in Fig.12 is easy to follow; once
during every cycle the programmed digits are jammed in
(15 616 in this example) and then a round number of
11 000 is jammed in, nine times in succession, by forcing
the JAM inputs via AND/OR gates.
Numbers larger than the extended counter range can also
be produced by cascading the PC74HC/HCT4059 with
some other counting devices. Figure 13 shows such an
arrangement where only one fixed divide-by number is
desired. The dual flip-flop wired to produce a divide-by-3
count can be replaced by other counters such as the “190”,
“191”, “192”, “193”, “4017”, “4510” and “4516”.
In Fig.13 the divide-by-n sub-system is preset once to a
number which represents the least significant digits of the
divide-by number (15 690 in the example shown in Fig.13).
The sub-system is then preset twice to a round number
(8 000 in the example shown in Fig.13) and multiplied by
the number of the divide-by mode (2 in the example shown
in Fig.13).
To verify:
15 690
+
2
×
8 000
×
2 = 47 690.
It is important that the second counting device has an
output that is HIGH or LOW during only one of its counting
states.
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