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參數(shù)資料
| 型號(hào)： | 74HCT40102 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Parallel-Load Shift Registers 16-SSOP -40 to 85 |
| 中文描述： | 8位同步BCD碼遞減計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 85K |
| 代理商： | 74HCT40102 |
December 1990
2
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
FEATURES
Cascadable
Synchronous or asynchronous preset
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40102 are high-speed Si-gate CMOS
devices and are pin compatible with the “40102” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40102 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40102” is
configured as two cascaded 4-bit BCD counters and has
control inputs for enabling or disabling the clock (CP), for
clearing the counter to its maximum count, and for
presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count
output (TC) are active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero ifTE is LOW, and remains LOW for
one full clock period.
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P
0
to P
7
) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P
0
to P
7
) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P
0
to P
7
) represent
two 4-bit BCD words.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
99) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 100 clock pulses long.
The “40102” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
APPLICATIONS
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP to TC
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
30
30
3.5
20
31
30
3.5
25
ns
MHz
pF
pF
notes 1 and 2
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|---|---|
| 74HCT40103N | 制造商:NXP Semiconductors 功能描述: |
| 74HCT40105 | 制造商:HAR 功能描述:74HCT40105 |
| 74HCT40105D | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105D,112 | 功能描述:寄存器 4-BIT X 16 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105D,118 | 功能描述:寄存器 4-BIT X 16 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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