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參數(shù)資料
| 型號： | 74HCT356 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Parallel-Load Shift Registers 16-SSOP -40 to 85 |
| 中文描述： | 8輸入多路復(fù)用器/冊;三態(tài) |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 74HCT356 |
December 1990
4
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
FUNCTION TABLE
Notes
1.
2.
3.
This column shows the input address set-up with LE = LOW (address latch is transparent).
CP is HIGH, LOW or
↓
.
D
0n
to D
7n
= data present at inputs D
0
to D
7
when the data latch clock made the transition from LOW-to-HIGH
D
0p
to D
7p
= data previously latched into the data latch by the LOW-to-HIGH transition of the data latch clock
H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH CP transition
↓
= HIGH-to-LOW CP transition
Z = high impedance OFF-state
INPUTS
OUTPUTS
DESCRIPTION
ADDRESS
(1)
CP
OUTPUT ENABLE
Y
Y
S
2
S
1
S
0
OE
1
OE
2
OE
3
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
↑
↑
↑
↑
↑
↑
↑
↑
(2)
(2)
(2)
(2)
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
D
0n
D
1n
D
2n
D
3n
D
4n
D
5n
D
6n
D
7n
D
0p
D
1p
D
2p
D
3p
D
4p
D
5p
D
6p
D
7p
Z
Z
Z
D
0n
D
1n
D
2n
D
3n
D
4n
D
5n
D
6n
D
7n
D
0p
D
1p
D
2p
D
3p
D
4p
D
5p
D
6p
D
7p
outputs in
high impedance
OFF-state
data is clocked
into latch
outputs do not
change states
(2)
(2)
(2)
(2)
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