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參數(shù)資料
| 型號： | 74HCT32 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HEADER, 10 POS,0.100 C, DUAL, RT ANG |
| 中文描述： | 四2輸入或門 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 35K |
| 代理商： | 74HCT32 |
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input OR gate
74HC/HCT32
FEATURES
Output capability: standard
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT32 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT32 provide the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
C
I
C
PD
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
C
L
= 15 pF; V
CC
= 5 V
6
3.5
16
9
3.5
28
ns
pF
pF
notes 1 and 2
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