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參數(shù)資料
| 型號(hào)： | 74HCT297 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital phase-locked-loop filter |
| 中文描述： | 數(shù)字鎖相環(huán)回路濾波器 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | 74HCT297 |
September 1993
10
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard/bus driver
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for
a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit
load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
EN
CTR
, D/U
A, B, C, D, K
CP,
φ
A
2
I/D
CP
,
φ
A
1
,
φ
B
0.3
0.6
1.5
AC CHARACTERISTICS FOR 74HCT
GND = 0 V, t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
I/D
CP
to I/D
OUT
propagation delay
φ
A
1
,
φ
B to XORPD
OUT
propagation delay
φ
B,
φ
A
2
to ECPD
OUT
output transition time
bus driver output
I/D
OUT
(pin 7)
output transition time
standard outputs
XORPD
OUT
, ECPD
OUT
(pins 11, 12)
clock pulse width
K
CP
clock pulse width
I/D
CP
set-up time
D/U, EN
CTR
to K
CP
hold time
D/U, EN
CTR
to K
CP
maximum clock pulse
frequency K
CP
maximum clock pulse
frequency I/D
CP
21
35
44
53
ns
4.5
Fig.11
t
PHL
/ t
PLH
16
32
40
48
ns
4.5
Fig.12
t
PHL
/ t
PLH
22
44
55
66
ns
4.5
Fig.13
t
THL
/ t
TLH
5
12
15
18
ns
4.5
Fig.11
t
THL
/ t
TLH
7
15
19
22
ns
4.5
Figs 12 and 13
t
W
16
8
20
24
ns
4.5
Fig.14
t
W
25
13
31
38
ns
4.5
Fig.11
t
su
24
13
30
36
ns
4.5
Fig.14
t
h
0
8
0
0
ns
4.5
Fig.14
f
max
30
62
24
20
MHz
4.5
Fig.14
f
max
20
36
16
13
MHz
4.5
Fig.11
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