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參數(shù)資料
| 型號： | 74HCT273 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器的復位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 58K |
| 代理商： | 74HCT273 |
September 1993
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
FEATURES
Ideal buffer for MOS microprocessor or memory
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
See “377” for clock enable version
See “373” for transparent latch version
See “374” for 3-state version
Output capability; standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
CP to Q
n
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
15
15
66
3.5
20
15
20
36
3.5
23
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
相關PDF資料 |
PDF描述 |
|---|---|
| 74HC273 | Octal D-type flip-flop with reset; positive-edge trigger |
| 74HC273 | Octal D Flip-Flop with Common Clock and Reset |
| 74HCT27 | 8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85 |
| 74HC27 | Triple 3-input NOR gate |
| 74HCT283 | 8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT273BQ | 制造商:NXP Semiconductors 功能描述:IC OCTAL D F-F POS-EDG DHVQ |
| 74HCT273BQ,115 | 功能描述:觸發(fā)器 OCTAL D-TYPE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT273BQ-G | 功能描述:觸發(fā)器 OCTAL D-TYPE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT273BQ-Q100X | 制造商:NXP Semiconductors 功能描述:74HCT273BQ-Q100/DHVQFN20/REEL7 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FLIP-FLOP OCT D POS 20DHVQFN |
| 74HCT273D | 功能描述:觸發(fā)器 OCTAL D F/F W/RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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