December 1990
2
Philips Semiconductors
Product specification
Quad bus transceiver; 3-state
74HC/HCT243
FEATURES
Non-inverting 3-state outputs
2-way asynchronous data bus communication
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT243 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT243 are quad bus transceivers featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
They are designed for 4-line asynchronous 2-way data
communications between data buses.
The output enable inputs (OE
A
and OE
B
) can be used to
isolate the buses.
The “243” is similar to the “242” but has non-inverting (true)
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
A
n
to B
n
;
B
n
to A
n
input capacitance
input/output capacitance
power dissipation capacitance per transceiver notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
6
11
ns
C
I
C
I/O
C
PD
3.5
10
26
3.5
10
34
pF
pF
pF