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參數資料
| 型號： | 74HCT237 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3-to-8 line decoder/demultiplexer with address latches(帶地址鎖存的3-8線譯碼器/多路分解器) |
| 中文描述： | 3至8線路解碼器/多路解復用器的地址鎖存器（帶地址鎖存的3-8線譯碼器/多路分解器） |
| 文件頁數： | 2/9頁 |
| 文件大?。?/td> | 68K |
| 代理商： | 74HCT237 |
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with
address latches
74HC/HCT237
FEATURES
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent
controls
Active HIGH mutually exclusive outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT237 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (A
n
). The “237”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “237” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E
1
and E
2
) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E
1
is LOW and E
2
is HIGH.
The “237” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
A
n
to Y
n
LE to Y
n
E
1
to Y
n
E
2
to Y
n
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
16
19
14
14
3.5
60
19
21
17
17
3.5
63
ns
ns
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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