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參數(shù)資料
| 型號(hào)： | 74HCT174N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP HEX D RESET 16DIP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 74HCT |
| 功能： | 主復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 6 |
| 頻率 - 時(shí)鐘： | 63MHz |
| 延遲時(shí)間 - 傳輸： | 21ns |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
1998 Jul 08
2
Philips Semiconductors
Product specication
Hex D-type ip-op with reset; positive-edge trigger
74HC/HCT174
FEATURES
Six edge-triggered D-type flip-flops
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb=25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
CP to Qn
17
18
ns
MR to Qn
13
17
ns
fmax
maximum clock frequency
99
69
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per flip-flop
notes 1 and 2
17
pF
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| 74HCT174PW | 功能描述:觸發(fā)器 HEX D-TYPE MASTER RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT174PW,112 | 功能描述:觸發(fā)器 HEX D-TYPE MASTER RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT174PW,118 | 功能描述:觸發(fā)器 HEX D-TYPE MASTER RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT174PW118 | 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| 74HCT174PW-Q100J | 制造商:NXP Semiconductors 功能描述:74HCT174PW-Q100/TSSOP16/REEL13 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FLIP-FLOP HEX D RESET 16TSSOP |
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