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參數(shù)資料
| 型號： | 74HCT173DB,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC QUAD D F-F POS-EDGE 16-SSOP |
| 產(chǎn)品培訓模塊： | Logic Packages |
| 標準包裝： | 78 |
| 系列： | 74HCT |
| 功能： | 主復位 |
| 類型： | D 型總線 |
| 輸出類型： | 三態(tài)非反相 |
| 元件數(shù)： | 4 |
| 每個元件的位元數(shù)： | 1 |
| 頻率 - 時鐘： | 80MHz |
| 延遲時間 - 傳輸： | 20ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 6mA，6mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | 568-2795-5 935189710112 |
December 1990
2
Philips Semiconductors
Product specication
Quad D-type ip-op; positive-edge trigger; 3-state
74HC/HCT173
FEATURES
Gated input enable for hold (do nothing) mode
Gated output enable control
Edge-triggered D-type register
Asynchronous master reset
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q0 to Q3)
and master reset (MR).
When the two data enable inputs (E1 and E2) are LOW, the
data on the Dn inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Qn
outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CP to Qn
MR to Qn
CL = 15 pF; VCC =5V
17
13
17
ns
fmax
maximum clock frequency
88
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per ip-op
notes 1 and 2
20
pF
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT173DB-T | 功能描述:觸發(fā)器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT173N | 制造商:NXP Semiconductors 功能描述:QUAD D-TYPE F/F 3-STATE |
| 74HCT173N,652 | 功能描述:觸發(fā)器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT173N652 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| 74HCT174 | 制造商:NTE Electronics 功能描述: |
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