參數(shù)資料
型號(hào): 74HCT153
廠商: NXP Semiconductors N.V.
英文描述: Dual 4-input multiplexer(雙4輸入多路復(fù)用器)
中文描述: 雙路4輸入多路復(fù)用器(雙4輸入多路復(fù)用器)
文件頁數(shù): 2/7頁
文件大?。?/td> 46K
代理商: 74HCT153
December 1990
2
Philips Semiconductors
Product specification
Dual 4-input multiplexer
74HC/HCT153
FEATURES
Non-inverting output
Separate enable for each output
Common select inputs
See ‘253” for 3-state version
Permits multiplexing from n lines to
1 line
Enable line provided for cascading
(n lines to 1 line)
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT153 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT153 have two
identical 4-input multiplexers which
select two bits of data from up to four
sources selected by common data
select inputs (S
0
, S
1
). The two 4-input
multiplexer circuits have individual
active LOW output enable inputs (1E,
2E) which can be used to strobe the
outputs independently. The outputs
(1Y, 2Y) are forced LOW when the
corresponding output enable inputs
are HIGH.
The “153” is the logic implementation
of a 2-pole, 4-position switch, where
the position of the switch is
determined by the logic levels applied
to S
0
and S
1
.
The logic equations for the outputs
are:
1Y = 1E.(1I
0
.S
1
.S
0
+1I
1
.S
1
.S
0
+
+1I
2
.S
1
.S
0
+1I
3
.S
1
.S
0
)
2Y = 2E.(2I
0
.S
1
.S
0
+2I
1
.S
1
.S
0
+
+2I
2
.S
1
.S
0
+2I
3
.S
1
.S
0
)
The “153” can be used to move data
to a common output bus from a group
of registers. The state of the select
inputs would determine the particular
register from which the data came. An
alternative application is a function
generator. The device can generate
two functions or three variables. This
is useful for implementing highly
irregular random logic.
The “153” is similar to the “253” but
has standard outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
1I
n
, 2I
n
to nY
S
n
to nY
nE to nY
input capacitance
power dissipation capacitance per multiplexer notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
14
15
10
3.5
30
16
17
11
3.5
30
ns
ns
ns
pF
pF
C
I
C
PD
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
(C
L
×
V
CC2
×
f
o
) = sum of outputs
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic
Package Information”
.
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