參數(shù)資料
型號: 74HC7046APW
廠商: NXP SEMICONDUCTORS
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, PDSO16
封裝: PLASTIC, TSSOP
文件頁數(shù): 27/38頁
文件大小: 468K
代理商: 74HC7046APW
December 1990
33
Philips Semiconductors
Product specication
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
Lock-detection circuit
The built-in lock-detection circuit will only work when used
in conjunction with the phase comparator PC2. The
lock-indication is derived from the phase error between
SIGIN and COMPIN. The PC2 has a typical phase error of
zero degrees over the entire VCO operating range.
However, to remain in-lock the circuit requires some small
adjustments. The variation is dependent on the loop
parameters and back-lash time (typically 5 ns). Depending
on the application, the phase error can be defined as the
limit, a phase error of greater magnitude would be
considered out-of-lock. An example of an in-lock detection
circuit using the “7046A” is shown in Fig.30.
If the PLL is in-lock, only very small pulses will come from
the “up” or “down” connections of PC2. These pulses are
filtered out by a RC network. A Schmitt trigger produces a
steady state level, a HIGH level indicates an in-lock
condition and a pulsed output indicates an out-of-lock
condition as shown in Fig.31.
Fig.30 An example of an in-lock detection circuit using the “7046A”.
See Fig.31 for input waveform.
Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.
(a)
(b)
相關PDF資料
PDF描述
74HCT7046ADB-T PHASE LOCKED LOOP, PDSO16
74HC7046APW-T PHASE LOCKED LOOP, PDSO16
74HCT7046ADB PHASE LOCKED LOOP, PDSO16
74HCT7046APW-T PHASE LOCKED LOOP, PDSO16
74HCT9046AP PHASE LOCKED LOOP, PDIP16
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