參數(shù)資料
型號： 74HC595
廠商： ON SEMICONDUCTOR
英文描述： 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
中文描述： 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊態(tài)輸出
文件頁數(shù)： 8/20頁
文件大?。?/td> 122K
代理商： 74HC595
1998 Jun 04
8
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: parallel outputs, bus driver, serial output, standard I
CC
category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITION
+
25
40 to
+
85
40 to
+
125
V
CC
(V)
WAVEFORMS
min
75
15
13
75
15
13
75
15
13
50
10
9.0
75
15
13
typ
max
min
95
19
16
95
19
16
95
19
16
65
13
11
95
19
16
max
min
110
22
19
110
22
19
110
22
19
75
15
13
110
22
19
max
t
PHL
/t
PLH
propagation delay
SH
CP
to Q
7
’
52
19
15
55
20
16
47
17
14
47
17
14
41
15
12
17
6
5
11
4
3
17
6.0
5.0
11
4.0
3.0
22
8
7
160
32
27
175
35
30
175
35
30
150
30
26
150
30
26
200
40
34
220
44
37
220
44
37
190
38
33
190
38
33
240
48
41
265
53
45
265
53
45
225
45
38
225
45
38
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
t
PHL
/t
PLH
propagation delay
ST
CP
to Q
n
ns
Fig.8
t
PHL
propagation delay
MR to Q
7
’
ns
Fig.10
t
PZH
/t
PZL
3-state output
enable time
OE to Q
n
ns
Fig.11
t
PHZ
/t
PLZ
3-state output
disable time
OE to Q
n
ns
Fig.11
t
W
shift clock pulse
width HIGH or
LOW
ns
Fig.7
t
W
storage clock
pulse width HIGH
or LOW
ns
Fig.8
t
W
master reset
pulse width LOW
ns
Fig.10
t
su
set-up time D
S
to
SH
CP
ns
Fig.9
t
su
set-up time SH
CP
to ST
CP
ns
Fig.8
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