I
參數(shù)資料
型號: 74HC58DB,112
廠商: NXP Semiconductors
文件頁數(shù): 2/5頁
文件大小: 0K
描述: IC DUAL AND-OR GATE 14-SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1,092
系列: 74HC
邏輯類型: 與/或門
電路數(shù): 2
輸入數(shù): 10 輸入(3,3,2,2)
施密特觸發(fā)器輸入:
輸出類型: 單端
安裝類型: 表面貼裝
封裝/外殼: 14-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 14-SSOP
包裝: *
December 1990
2
Philips Semiconductors
Product specication
Dual AND-OR gate
74HC58
FEATURES
Output capability: standard
ICC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
1n to 1Y
11
ns
2n to 2Y
9
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per
gate
notes 1 and 2
18
pF
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