參數(shù)資料
型號(hào): 74HC4094
廠商: System Logic Semiconductor Co., Ltd.
英文描述: 8-Bit Serial-Input Shift Register With Latched 3-State Outputs(High-Performance Silicon-Gate CMOS)
中文描述: 8位串行輸入鎖存移位寄存器與三態(tài)輸出(高性能硅柵CMOS)
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 72K
代理商: 74HC4094
December 1990
6
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min. typ. max. min. max. min.
max.
t
PHL
/ t
PLH
propagation delay
CP to QS
1
50
18
14
44
16
13
63
23
18
58
21
17
55
20
16
41
15
12
19
7
6
14
5
4
14
5
4
14
5
4
28
10
8
150
30
26
135
27
23
195
39
33
180
36
31
175
35
30
125
25
21
75
15
13
190
38
33
170
34
29
245
49
42
225
45
38
220
44
37
155
31
26
95
19
16
225
45
38
205
41
35
295
59
50
270
54
46
265
53
45
190
38
32
110
22
19
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
Fig.7
t
PHL
/ t
PLH
propagation delay
CP to QS
2
ns
Fig.7
t
PHL
/ t
PLH
propagation delay
CP to QP
n
ns
Fig.7
t
PHL
/ t
PLH
propagation delay
STR to QP
n
ns
Fig.8
t
PZH
/ t
PZL
3-state output enable time
OE to QP
n
ns
Fig.9
t
PHZ
/ t
PLZ
3-state output disable
time OE to QP
n
ns
Fig.9
t
THL
/ t
TLH
output transition time
ns
Fig.7
t
W
clock pulse width
HIGH or LOW
80
16
14
80
16
14
50
10
9
100
20
17
100
20
17
100
20
17
65
13
11
125
25
21
120
24
20
120
24
20
75
15
13
150
30
26
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
t
W
strobe pulse width
HIGH
ns
Fig.8
t
su
set-up time
D to CP
ns
Fig.10
t
su
set-up time
CP to STR
ns
Fig.8
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