參數(shù)資料
型號： 74HC4059N3
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Programmable divide-by-n counter
中文描述： HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PDIP24
封裝： 0.300 INCH, PLASTIC, SOT-222-1, MS-001AF, DIP-24
文件頁數(shù)： 4/20頁
文件大?。?/td> 147K
代理商： 74HC4059N3
1998 Jul 08
4
Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP to Q
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V 18
20
40
3.5
32
ns
MHz
pF
pF
40
3.5
30
notes 1 and 2
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC4059N3;
74HCT4059N3
74HC4059N;
74HCT4059N
74HC4059D;
74HCT4059D
DIP24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
DIP24
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
相關(guān)PDF資料
PDF描述
74HCT4059N3 Programmable divide-by-n counter
74HCT4059 Programmable divide-by-n counter
74HC4059 Programmable divide-by-n counter
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