參數(shù)資料
型號(hào): 74HC4046
廠商: NXP Semiconductors N.V.
英文描述: Phase-locked-loop with VCO
中文描述: 鎖相環(huán)與VCO的環(huán)
文件頁數(shù): 31/34頁
文件大?。?/td> 467K
代理商: 74HC4046
1997 Nov 25
31
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
PLL design example
The frequency synthesizer, used in
the design example shown in Fig.32,
has the following parameters:
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
settling time
:
overshoot
:
1 ms
<
20%
The open-loop gain is
H (s) x G (s) = K
p
×
K
f
×
K
o
×
K
n
.
Where:
K
p
= phase comparator gain
K
f
= low-pass filter transfer gain
K
o
= K
v
/s VCO gain
K
n
= 1/n divider ratio
The programmable counter ratio
K
n
can be found as follows:
f
f
step
The VCO is set by the values of R1,
R2 and C1, R2 = 10 k
(adjustable).
The values can be determined using
the information in the section
“DESIGN CONSIDERATIONS”.
With f
o
= 2.5 MHz and f
L
= 500 kHz
this gives the following values
(V
CC
= 5.0 V):
R1 = 10 k
R2 = 10 k
C1 = 500 pF
N
min.
----------
100 kHz
-2 MHz
20
=
=
=
N
max.
f
f
step
----------
100 kHz
-3 MHz
30
=
=
=
The VCO gain is:
The gain of the phase
comparator is:
V
4
π
×
The transfer gain of the filter is
given by:
1
τ
s
+
1
τ
1
+
+
Where:
τ
1
=
The characteristics equation is:
1 + H (s)
×
G (s) = 0.
This results in:
1
+
----------------------------------K
+
The natural frequency
ω
n
is
defined as follows:
×
1
+
K
v
2f
π
0.9
×
V
CC
0.9
(
)
-----------------------2
˙
=
=
3.2
1 MHz
2
π
2
10
6
×
×
r/s/V
=
K
p
------------
0.4 V/r.
=
=
K
f
τ
2
(
)
s
------------------------------------.
=
R3C2 and
τ
2
R4C2.
=
s
2
K
K
+
n
)
τ
2
×
τ
2
τ
1
(
K
--------------------------K
K
+
n
2
1
0.
=
ω
n
p
K
K
v
K
n
)
×
τ
2
(
=
and the damping value
ζ
is defined as
follows:
1
K
+
In Fig.33 the output frequency response to
a step of input frequency is shown.
The overshoot and settling time
percentages are now used to determine
ω
n
. From Fig.33 it can be seen that the
damping ratio
ζ
= 0.45 will produce an
overshoot of less than 20% and settle to
within 5% at
ω
n
t = 5. The required settling
time is 1 ms.
This results in:
5
t-
0.001
Rewriting the equation for natural
frequency results in:
K
-------------------------------.
=
The maximum overshoot occurs at N
max
.:
When C2 = 470 nF, then
τ
+
K
p
now R3 can be calculated:
τ
1
C2
ζ
2
ω
n
--1
K
+
n
)
τ
2
×
τ
2
τ
1
----------------------------------K
×
=
ω
n
----5
5
10
3
×
r/s.
=
=
=
τ
1
τ
2
+
(
)
K
ω
n
K
2
τ
1
τ
2
+
(
)
5000
2
2
10
6
30
×
×
×
0.4
0.0011 s.
=
=
R4
×
×
ω
n
×
ζ
1
×
C2
×
K
n
K
v
-----------------------------2
315
=
=
R3
-------
R4 = 2 k
.
=
相關(guān)PDF資料
PDF描述
74HC4046A Phase-locked-loop with VCO
74HC4046 Phase-Locked Loop
74HC4046 CMOS Phase Lock Loop
74HC4046 Phase-Locked Loop
74HCT4052 Dual 4-channel analog multiplexer/demultiplexer(雙四通道模擬多路復(fù)用器/多路分解器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74HC4046AD 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC4046AD,652 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC4046AD,653 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC4046AD 制造商:NXP Semiconductors 功能描述:74HC CMOS SMD 74HC4046 SOIC16
74HC4046AD/AUJ 制造商:NXP Semiconductors 功能描述:74HC4046AD/SO16/REEL13//AU - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC PHASE LOCK LOOP W/VCO 16SOIC