參數(shù)資料
型號(hào): 74HC4040
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 12-stage binary ripple counter
中文描述: 12位的二進(jìn)制紋波計(jì)數(shù)器
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 137K
代理商: 74HC4040
74HC_HCT4040_3
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 14 September 2005
15 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
13. Waveforms
t
PHL
propagation delay MR to Qn
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
V
CC
= 4.5 V; C
L
= 50 pF;
see
Figure 8
-
-
68
ns
t
THL
, t
TLH
output transition time
-
-
22
ns
t
W
clock pulse width HIGH or LOW
24
-
-
ns
master reset pulse width; HIGH
24
-
-
ns
t
rec
recovery time MR to CP
15
-
-
ns
f
max
maximum operating frequency
20
-
-
MHz
Table 10:
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see
Figure 9
.
Symbol
Parameter
Dynamic characteristics for type 74HCT4040
…continued
Conditions
Min
Typ
Max
Unit
74HC4040: V
M
= 50 %; V
I
= GND to V
CC
.
74HCT4040: V
M
= 1.3 V; V
I
= GND to 3 V.
Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition
times, maximum clock pulse frequency, master reset (MR) pulse width, master
reset to output (Qn) propagation delays and master reset to clock (CP) removal
time.
Fig 8.
MR input
CP input
Q0 or Qn
output
t
W
t
PHL
1/f
max
t
rem
V
M
V
I
V
I
V
M
001aad590
t
PLH
t
W
t
TLH
t
THL
t
PHL
V
M
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